Presentations and Articles:
- Semiconductor.net: Test Socket Industry Faces Issues Scaling Below 0.4 mm Pitch, 08.04.08, contributing remarks by Ila Pal and Dr. James Forster
- Thermal Simulation Dramatically Reduces Time to Design Complex Burn-in Test System, Trevor Moody, Mechanical and Thermal Engineer, MEPTEC Report, 2008
- BiTS 2008: An Examination of the Causes of Cres Degradation Which Effect the Life of a Socket, Nick Langston, Jr.
- BiTS 2008: Finite Element Analysis Using Elastic Membrane Technique for Test Socket Design Optimization, (Praba) K. Prabakaran, Ila Pal
- ITC 2007: Solving Test Problems of High Speed, High Density IC Packages Using an Innovative Test Contactor, Ila Pal, Aristotle Querubin
- MAPS 2007: The Effect of Package Pin Map on Signal Integrity for Test Applications - presentation /paper, Hongjun Yao (presenter), James Zhou, James Forster
- KGD Packaging and Test Workshop 2007: WLCSP Test Solutions Using Small-pitch Spring Pins, James Zhou, Sr. Technical Staff (presenter), Hongjun Yao Ph.D, James Forster Ph.D, Nick Langston Sr.
- Integrating Thermal Management and Burn-in Operations: Thermal Dissipation and Power Variance Prevention - (as featured in the October 2007 issue of Advanced Packaging),by Chris Lopez, Manager, Thermal Solutions
- BiTS 2007: Elastomeric Interconnets
- BiTS 2007: Signal Integrity
- BiTS 2007: Minimizing Socket & Board Inductance using a Novel decoupling Interposer
- BiTS 2007: From the Frying Pan into the Fire: Working on Both Sides of the Tooling Supply Chain
- BiTS 2006: Thermal Control Units: Development of an Analytical Model and Experimental Validation to Optimize the Voltage Input
- DCI's presentation at Agilent for High Speed Simulation of ATE Interfaces
Call 408.988.6800 if you are interested in this topic or would like to schedule a seminar at your site.
- Signal Losses in Gigabit PC Boards
- Optimizing Contactors for High-performance Test Sockets (Advanced Packaging)
- IDDQ Testing for Very Deep Sub-Micron Devices Can Reduce Burn-In and Test Equipment Costs
(Chip Scale Review, April 2004)
Integrated Design of Custom Sockets And Load Boards (Evaluation Engineering, 2002)
- Chip Scale Package Burn-In Socket Technology as Pitches Move 0.5mm, (Future Fab International, 2000)
